Electrically erasable programmable read only memory (EEPROM) structures are commonly used in integrated circuits for non-volatile data storage. As is known, EEPROM device structures commonly include a floating gate that has charge storage capabilities. Charge can be forced into the floating gate structure or removed from the floating gate structure using control voltages. The conductivity of the channel underlying the floating gate is significantly altered by the presence of charges stored in the floating gate. The difference in conductivity due to a charged or uncharged floating gate can be current sensed, thus allowing binary memory states to be determined. The conductivity difference is also represented by shift in the threshold voltage (Vt) associated with the device in the two different states.
As semiconductor devices continue to evolve, the operating voltages of such semiconductor devices are often reduced in order to suit low power applications. It is desirable for such operating voltage reductions to be accomplished while ensuring that the speed and functionality of the devices is maintained or improved. A controlling factor in the operating voltages required to program and erase devices that include floating gates is the thickness of the tunnel oxide through which carriers are exchanged between the floating gate and the underlying channel region.
In many prior art device structures, the floating gate is formed from a uniform layer of conducting or semiconducting material such as polysilicon. In such prior art device structures, a thin tunnel dielectric layer beneath the floating gate presents the problem of charge leakage from the floating gate to the underlying channel through defects in the thin tunnel dielectric layer. Such charge leakage can lead to degradation of the memory state stored within the device and is therefore undesirable. In order to avoid such charge leakage, the thickness of tunnel dielectric is often increased. However, thicker tunnel dielectric requires higher (programming and erasing) voltages for storing and removing charge from the floating gate as the charge carriers must pass through the thicker tunnel dielectric. In many cases, higher programming voltages require the implementation of charge pumps on integrated circuits in order to increase the supply voltage to meet programming voltage requirements. Such charge pumps consume a significant amount of die area for the integrated circuit and therefore reduce the memory array area efficiency and increase overall costs.
In order to reduce the required thickness of the tunnel dielectric and improve the area efficiency of the memory structures by reducing the need for charge pumps, the uniform layer of material used for the floating gate may be replaced with a plurality of nanoclusters, which operate as isolated charge storage elements. Such nanoclusters are also often referred to as nanocrystals, as they may be formed of silicon crystals. In combination, the plurality of nanoclusters provides adequate charge storage capacity while remaining physically isolated from each other such that any leakage occurring with respect to a single nanocluster via a local underlying defect does not cause charge to be drained from other nanoclusters. That is, by controlling average spacing between nanoclusters, it can be ensured that there is no lateral charge flow between nanoclusters in the floating gate. As such, thinner tunnel dielectrics can be used in these device structures. The effect of leakage occurring in such thin tunnel dielectric devices does not cause the loss of state information that occurs in devices that include a uniform-layer floating gate.
A limiting factor in fabrication of devices that include floating gates made up of a plurality of nanoclusters relates to controlling size, density, and uniformity of the nanoclusters within the floating gate structure. The density of the nanoclusters is important in the determination of the change in the threshold voltage for the device between the states where the floating gate is charged or discharged. Higher densities are desirable as they lead to an increased change in threshold voltage when the density of charges per storage element is fixed. Prior art techniques for forming nanoclusters on the oxide tunnel dielectric were limited to a density as low as 5(1011) nanoclusters per cm2. More recently, nanocluster densities of 1(1012) nanoclusters per cm2 have been reported. With such a limited density of isolated storage elements, the charge density per nanocluster, or number of carriers that each nanocluster must retain, is forced to an elevated level. The higher storage density per nanocluster presents difficulties in storing (i.e., programming) a high number of electrons due to quantum confinement. In contrast to this limitation of higher nanocluster densities, lower nanocluster densities yields a smaller programming window at a given programming time. Furthermore, the programming time required for adding subsequent carriers continues to increase as the charge density per nanocluster is elevated. Even increasing the programming time may be insufficient to produce a proper number of carriers.
In one prior art technique for forming silicon nanoclusters, ion implantation is used to implant silicon atoms into a dielectric material. Following implantation, an annealing step causes these implanted silicon atoms to group together through phase separation to form the nanoclusters. Problems arise using such a technique due to the difficulty in controlling the depth at which the silicon nanoclusters are formed due to the phase segregation in the dielectric material. Since the depth at which the isolation storage elements are formed dramatically affects the electrical characteristics of the resulting device, ion implantation does not provide the level of control desired in a manufacturing situation.
In another prior technique for forming the silicon nanoclusters, a thin layer of amorphous silicon is deposited on the tunnel dielectric material. A subsequent annealing step is used to recrystallize the amorphous silicon into the nanoclusters. In order to produce nanoclusters of a desired density and size, the layer of amorphous silicon should be deposited such that it is on the order of 7-10 angstroms in thickness. Deposition of such thin layers of amorphous silicon is hard to control and therefore impractical in a manufacturing process. In addition to such control issues, additional problems may arise due to preexisting crystalline zones within the amorphous silicon layer. Such preexisting crystallites serve as nucleation sites for crystal growth, which deleteriously interferes with the spontaneous crystal growth desired for formation of the nanoclusters.
In other prior techniques for forming nanoclusters, chemical vapor deposition (CVD) techniques such as low pressure chemical vapor deposition (LPCVD) are used to nucleate and grow the nanoclusters directly on the tunnel oxide. Such prior art LPCVD techniques typically involve a very short deposition time period, on the order of approximately 10 to 30 seconds. Part of this deposition time period includes an incubation period where an adequate number of silicon atoms are generated on the surface of the dielectric prior to the commencement of the clustering activity that forms the crystalline structures of the nanoclusters. The remaining portion of the time is used to nucleate and grow the nanoclusters to the desired size. Due to the fact that the time period associated with nucleation and growth is so short, slight deviations in the processing parameters have profound effects on the resulting density and size uniformity of the resulting nanoclusters. Moreover, systematic effects can be significant. For example, portions of a silicon wafer being processed that are near the source of the reactant gas may realize a much higher density and size of nanoclusters, whereas portions of the wafers that are more distant from the reactant gas source would see lower densities and smaller sizes of nanoclusters. Such process non-uniformities are undesirable in manufacturing processes.
Prior art techniques exist only to grow semiconductor nanoclusters or nanocrystals. There is no known method to grow metallic nanodots around semiconductor nucleation points (i.e., the nuclei). Existing methods known to exist are merely based on metallic physical vapor deposition (PVD) coatings such as a de-wetting phenomena which occurs during an anneal step or, alternatively, a single-step metallic CVD deposition. However, neither of these techniques allow control of nanocluster density nor nanocluster size.
Advantages of metallic nanodots, as compared with semiconductor nanocrystals, include an ability to store more electrons (e.g., in a flash memory application) since little or no quantum confinement will occur. Therefore, a need exists for a method for including metallic nanoclusters within semiconductor devices in a manner that provides a high density of storage elements while maintaining control over the size dispersion of the storage elements.